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Chapter 25 External Interrupt
8.Caution
8. Caution
• When the request input is a level (LAn, LBn = “00” or “01”) and when the INT pin input is the set active level,
the corresponding bit (ERn) will be re-set to “1” even if the external interrupt request bit (ERn) is set to “0”.
Note: n = 0 to 15
• Before enabling the external interrupt request with ENn = “1” it is recommended to clear the external
interrupt request bit (set ERn to “0”) to avoid interrupts caused by previous matches of the input trigger (the
IRQ flag is set independently of the setting of ENn).
Note: n = 0 to 15
• Before going into standby (stop mode), make sure to disable unused external interrupts (ENn = “0”).
Note: n = 0 - 15
• Minimum 3x CLKP (peripheral clock) is required for the pulse width to detect the edge presence when the
request level is set to the edge request.
• When waking up from STOP mode with edge detection enabled a minimum pulse width (> 50ns) of the INT
signal trigger must be fulfilled.
• The interrupt request to the interrupt controller remains active even if an external interrupt request is input
from the external interrupt pin INTn and canceled afterward, since the interrupt request flag (ERn) is present.
To cancel the interrupt request to the interrupt controller, the interrupt request flag must be cleared (ERn =
“0”) with software. (See the diagram in “5. Operation (Page No.327)”)
Note: n = 0 to 15