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Chapter 33 I2C Controller
2.I2C Interface Registers
• a repeated start condition is generated by another master in the first bit of a data byte
• the interface could not generate a start or stop condition because another slave pulled the SCL line low
before
[bit 4] LRB (Last Received Bit)
This bit is used to store the acknowledge message from the receiving side at the transmitter side.
It is changed by the hardware upon reception of bit 9 (acknowledge bit) and is also cleared by a start or stop
condition.
[bit 3] TRX (Transferring data)
This bit indicates data sending operation during data transfer.
It is set to ‘1’:
• if a start condition was generated in master mode at the end of a first byte transfer and read access as slave
or sending data as master
It is set to ‘0’ if:
• the bus is idle (BB=‘0’ in IBCR0)
• an arbitration loss occured
• a ‘1’ is written to the SCC bit during master interrupt (MSS=‘1’ and INT=‘1’)
• the MSS bit is cleared during master interrupt (MSS=‘1’ and INT=‘1’)
• the interface is in slave mode and the last transferred byte was not acknowledged
• the interface is in slave mode and it is receiving data
• the interface is in master mode and is reading data from a slave
[bit 2] AAS (Addressed As Slave)
This bit indicates detection of a slave addressing.
This bit is cleared by a (repeated-) start or stop condition. It is set if the interface detects its seven and/or ten
bit slave address.
[bit 1] GCA (General Call Address)
This bit indicates detection of a general call address (0x00).
0 Receiver acknowledged.
1 Receiver did not acknowledge.
0 Not transmitting data.
1 Transmitting data.
0 Not addressed as slave.
1 Addressed as slave.
0 General call address not received as slave.