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Chapter 38 Reload Timer
3.Configuration
Figure 3-2 Configuration Diagram
Figure 3-3 Register List
Note: For information about ICR registers and interrupt vectors, see “Chapter 24 Interrupt Control (Page
No.311)”.
Selector
CSL2-0
110
TMCS R:bit12-10
MO D2- 0
0
0
1
10
11
0
XX
----------
TMCS R:bit9-7
CNTE TMCS R:bit1
0
1
Stop count
Enable count
TRG TMCSR:bit0
0
1
No effect
Soft trigger
TMR0
TMRLR0
16 bit reload register
16 bit down counter
//
Underflow
Reload
Event source
.
Counter
activation
Stop
"H" square wave during count
"L" square wave during count
"L" toggle output on count start
"H" toggle output on count start
One-shot mode
Reload mode
OUTL
0
0
RELD TMCSR: bit5, bit4
1
0
11
1
0
Stop
Trigger (reload + counter activation)
* For internal clock, see the previous chart.
Active edge
1
Latch,
output
change
0
Reload
INTE TMCSR:bit3
0
1
Disable interrupts
Enable interrupts
1
Timer interrupt
(underflow)
UF TMCSRx:bit2
0
1
Underflow not present
Underflow generation
WRITE 0: Flag clear
0
Reload timer 0 (External event count)
External event *
0
0
1
10
11
0
XX
----------
Rising edge
Falling edge
Both edges
Disabled
Reload/activation/stop
control circuit
0
0
0
0
1
To general-purpose
port input
To general-purpose
port input
From general-purpose
port output
From general-purpose
port output
TIN0/ICU0/P14.0
PFR14.0
0
1
0
1
GP Port
Reload Timer Input
TIN0
TOT0
0
1
OCU0 output
TOT0 output
TOT0/OCU0/P15.0
Ch01 -> PPG0-PPG1
EPFR15.0