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Chapter 24 Interrupt Control
6.Setting
6. Setting
*: For the setting procedure, refer to the section indicated by the number.
7. Q & A
7.1 How can I set interrupt levels?
Set by Interrupt control registers (ICR00 to ICR63).
It is necessary to set interrupt levels in advance to the control registers of the applicable interrupts.
• Since the bit of the interrupt control register (ICR[4]) is fixed to “1”, 0 to 15 cannot be set to a register.
7.2 How do I enable interrupts?
To enable interrupts, all of the following three settings should be set:
• Set the value 16 to 30 to the applicable register in the interrupt control registers (ICR00-ICR63).
• Set the interrupt request enabling bit of the applicable peripheral function to “1” (enable) (See the chapter
for the corresponding peripheral function).
• Set the interrupt enabling flag (I) to “1.”
7.3 How do I disable interrupts?
To disable interrupts, at least one of the following three settings should be set:
• Set the value 31 to the applicable register in the interrupt control registers (ICR00-ICR63).
• Set the interrupt request enabling bit of the applicable peripheral function to “0” (disable).
• Set the interrupt enabling flag (I) to “0” (disable all interrupts.)
Table 6-1 Setting Required to Use Interrupts
Setting Setting Registers
Setting
Procedure
Setting the interrupt level Interrupt control registers (ICR00 to ICR63) See 7.1
Clearing the interrupt request flags See the corresponding chapter for each peripheral function. –
Enabling interrupt requests See the corresponding chapter for each peripheral function. –
I flag setting CCR register See 7.5
Table 6-2 Setting that Requires the Setting within Interrupt Processing
Setting Setting Registers
Setting
Procedure
Clearing the interrupt request flags See the corresponding chapter for each peripheral function. –
Interrupt control registers ICR00 to ICR63
How to specify the highest level Set 16.
How to specify a level Set any level (from 16 to 30).
How to specify the lowest level Set 30.
When interrupt is not used Set 31 (interrupt disable).