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Chapter 26 DMA Controller
3.DMA Controller (DMAC) Operation
Even if DREQ is reasserted earlier, it is ignored because the transfer has not been completed. If no transfer
requests for other channels occur, transfer over the same channel is restarted by reasserting DREQ when the
DACK pin output is asserted.
■ Timing of DACK Pin Output
The DACK output of this DMAC indicates that transfer with respect to an accepted transfer request is being
performed.
The output of DACK is basically synchronized with the address output of external bus access timing. To use
DACK output, it is necessary to enable the DACK output with a port.
■ Timing of the DEOP Pin Output
• The DEOP output of this DMA indicates that DMA transfer for the specified number of times of the accepted
channel has been completed.
• DEOP output is output when access to an external area of the last transfer block starts. Thus, if any value
other than 1 is set (block transfer mode) as the block size, DEOP is output when the last data of the last block
is transferred. In this case, the acceptance of the next DREQ is already started even during transfer (before
DEOP output) if the DACK pin output is asserted.
• The DEOP output is synchronized with RD and WRn of external bus access timing. However, if the transfer
source/transfer destination is internal access, DEOP is not output. To use DEOP output, it is necessary to
enable the DEOP output using the port register.
■ If an External Pin Transfer Request is Reentered During Transfer
● For burst, step, and block transfers
While the DACK signal is asserted within the DMAC, the next transfer request, if it is entered, is disabled.
However, since operation of the external bus control unit and operation of the DMAC are not completely
synchronous, the circuit must be initialized to create DREQ pin input using DACK and DEOP output to enable
transfer requests by using DREQ input.
● For a demand transfer
If reloading of the transfer count register is specified when transfer for as many transfers as specified has been
completed, another transfer request is accepted.
■ If Another Transfer Request Occurs During Block Transfer
No request is detected before the transfer of the specified blocks is completed. At the block boundaries, transfer
requests accepted at that time are evaluated and then transfer on the channel with the highest priority is
performed.
■ Transfer Between External I/O and External Memory
As targets of transfer by the DMAC, external I/O and external memory are not distinguished. Specify an external
I/O as a fixed external address.
To perform fly-by transfer, set the address of external memory in the transfer destination address register. For
external I/O, use DACK output and the signal decoded by the read signal RD or write signal WRn pin.