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Chapter 34 CAN Controller
2.Register Description
If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest
priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it. If
IntId is different from 0x0000 and IE is set, the interrupt line to the CPU is active. The interrupt line remains
active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
The Status Interrupt has the highest priority. Among the message interrupts, the Message Object’ s interrupt
priority decreases with increasing message number.
A message interrupt is cleared by clearing the Message Object’s IntPnd bit. The Status Interrupt is cleared by
reading the Status Register.
■ Transmission Request Registers (TREQR)
These registers hold the TxRqst bits of the 32 Message Objects. By reading out the TxRqst bits, the CPU can
check for which Message Object a Transmission Request is pending. The TxRqst bit of a specific Message
Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message Handler after
reception of a Remote Frame or after a successful transmission.
0x8001-
0xFFFF
unused.
TxRqst32-1 Transmission Request Bits (of all Message Objects)
0 This Message Object is not waiting for transmission.
1 The transmission of this Message Object is requested and is not yet done.
TxRqst32-25
⇐ Bit no.
Read/write ⇒
(R) (R) (R) (R) (R) (R) (R) (R)
Default value⇒
(0) (0) (0) (0) (0) (0) (0) (0)
Transmission Req Register 2 high byte
Address : Base + 0x80
H
15 14 13 12 11 10 9 8
TREQR2H
TxRqst24-17
⇐ Bit no.
Read/write ⇒
(R) (R) (R) (R) (R) (R) (R) (R)
Default value⇒
(0) (0) (0) (0) (0) (0) (0) (0)
Address :
Base + 0x
81H
765432 10
TREQR2L
Transmission Req Register 2 low byte
TxRqst16-9
⇐ Bit no.
Read/write ⇒
(R) (R) (R) (R) (R) (R) (R) (R)
Default value⇒
(0) (0) (0) (0) (0) (0) (0) (0)
Transmission Req Register 1 high byte
Address : Base + 0x82
H
15 14 13 12 11 10 9 8
TREQR1H
TxRqst8-1
⇐ Bit no.
Read/write ⇒
(R) (R) (R) (R) (R) (R) (R) (R)
Default value⇒
(0) (0) (0) (0) (0) (0) (0) (0)
Address :
Base + 0x
83H
765432 10
TREQR1L
Transmission Req Register 1 low byte