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Chapter 11 Memory Controller
8.Explanations of Registers
• BIT[7]: FLUSH - Flush instruction cache entries
This bit is set after reset.
If the FLUSH bit is set, the instruction cache entries are flushed sequentially. During this initialization the cache is
disabled. The initialization has a duration of 1 clock cycle per cache entry. The number of valid entries depends on
the configured cache size.
After completion (all entries are flushed) the FLUSH bit is cleared by hardware.
Writing a ’1’ to this bit triggers the flushing of the cache entries.
Important remark: It is not allowed to set the cache size configuration (FCHCR.SZ[1:0]) and FLUSH at the same
time (same write access). Always first set the size configuration before flushing the cache.
• BIT[6]: DBEN - Data Buffer ENable
This bit is cleared after reset. The read data buffer is disabled by default.
Setting the DBEN bit enables the data read buffer. This is useful to speed up reading of data structures of 8 or 16
bit operands. There is one word data buffer implemented. If the same 32 or 64 bit word address is accessed con-
secutively, the data is read from the buffer.
(Data buffer is not available on MB91460 series)
• BIT[5]: PFEN - PreFetch ENable
This bit is cleared after reset. The prefetch of instructions is disabled by default.
Setting the PFEN bit enables the code prefetch from the next word on instruction address IA+4. Prefetch eliminates
any latency in the code fetch path of the MCU to the FLASH memory for linear code.
When switching on 64 bit read mode (RD64=1) then prefetch will be performed on instruction address IA+8 (when
current access is aligned at IA+0) and on instruction address IA+4 (when current access is aligned at IA+4). How-
ever, the setting of PF2I=1 in the 64 bit read mode will cause a prefetch only on next instruction address IA+4 (in-
dependent of current access alignment is IA+0 or IA+4).
A running prefetch cycle can be directly taken over from a matching instruction access. If there is no instruction ac-
cess in between, the prefetched instruction word is stored in cache memory. If there is an FLASH access (code or
data) to an address different from the prefetch address, the prefetch cycle is canceled immediately.
0 Flushing the instruction cache entries has been completed
1 Actually flushing the instruction cache entries
0 Buffering of read data is disabled (default)
1 Buffering of read data is enabled
0 Prefetch of instructions is disabled (default)
1 Prefetch of instructions is enabled