Filter
Top Products
686
Chapter 33 I2C Controller
3.I2C Interface Operation
■ Slave Address Masking
Only the bits set to ‘1’ in the mask registers (ITMK0 / ISMK0) are used for address comparision, all other bits
are ignored. The received slave address can be read from the ITBA0 (if ten bit address received, RAL=‘1’) or
ISBA0 (if seven bit address received, RAL=‘0’) register if the AAS bit in the IBSR0 register is ‘1’.
If the bitmasks are cleared, the interface can be used as a bus monitor since it will always be addressed as
slave. Note that this is not a real bus monitor because it acknowledges upon any slave address reception,
even if there is no other slave listening.
■ Addressing Slaves
In master mode, after a start condition is generated the BB and TRX bits are set to ‘1’ and the contents of the
IDAR0 register is sent in MSB first order. After address data is sent and an acknowledge signal was received
from the slave device, bit 0 of the sent data (bit 0 of the IDAR0 register after sending) is inverted and stored in
the TRX bit. Acknowledgement by the slave may be checked using the LRB bit in the IBSR0 register. This
procedure also applies to a repeated start condition.
In order to address a ten bit slave for write access, two bytes have to be sent. The first one is the ten bit
address header which consists of the bitsequence ‘1 1 1 1 0 A9 A8 0’, it is followed by the second byte
containing the lower eight bits of the ten bit slave address (A7 - A0).
A ten bit slave is accessed for reading by sending the above byte sequence and generating a repeated start
condition (SCC bit in IBCR0) followed by a ten bit address header with read access (1 1110A9A81).
Summary of the address data bytes:
7 bit slave, write access: Start condition - A6 A5 A4 A3 A2 A1 A0 0.
7 bit slave, read access: Start condition - A6 A5 A4 A3 A2 A1 A0 1.
10 bit slave, write access: Start condition - 1 1110A9A80 - A7 A6 A5 A4 A3 A2 A1 A0.
10 bit slave, read access: Start condition - 1 1 1 1 0 A9 A8 1 - A7 A6 A5 A4 A3 A2 A1 A0 - repeated start -
11110A9A81.
■ Arbitration
During sending in master mode, if another master device is sending data at the same time, arbitration is
performed. If a device is sending the data value ‘1’ and the data on the SDA line has an ‘L’ level value, the
device is considered to have lost arbitration, and the AL bit is set to ‘1.’ Also, the AL bit is set to ‘1’ if a start
conditon is detected at the first bit of a data byte but the interface did not want to generate one or the
generation of a start or stop condition failed by some reason.
Arbitration loss detection clears both the MSS and TRX bit and immediately places the device in slave mode
so it is able to acknowledge if its own slave address is being sent.
■ Acknowledgement
Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR0 register can be used
to select whether to send an acknowledgment when data bytes are received.
When data is send in slave mode (read access from another master), if no acknowledgement is received from
the master, the TRX bit is set to ‘0’ and the device goes to receiving mode. This enables the master to
generate a stop condition as soon as the slave has released the SCL line.
In master mode, acknowledgement by the slave may be checked by reading the LRB bit in the IBSR0 register.