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Chapter 16 Clock Supervisor
4.Operation Modes
Figure 4-9 Timing Diagram: Sub-clock missing in main clock mode, SRST=1
PONR
MCLK
SCLK
RC_CLK
OSC_STAB
MSVE
MSEN
SSVE
SSEN
MCLK_STBY
SCLK_STBY
TO_MCLK
TO_SCLK
EXT_RST
EXT_RST_OUT
MCLK_OUT
SCLK_OUT
MCLK_MISSING
SCLK_MISSING
SRST
Clock Mode
Main Main
Sub