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Chapter 5 CPU Registers
2.Dedicated Registers
■ Caution: PS Register
Since some instructions have already processed PS register in advance, the following exception operations may break
interrupt processing routine during the use of debugger, or update PS flag data.
In either cases, after returning from EIT, it is designed to execute the correct process so that operations before and
after EIT will be processed in accordance with specification.
• At instruction right before DIV0U/DIV0S instruction, the following 1. to 3. operation may be executed.
• If user interrupt is received,
• If step execution is executed,
• If data event or emulator menu is broken,
1. D0 or D1 flag is updated in first.
2. EIT processing routine (user interrupt or emulator) is executed.
3. After returning from EIT, it executes DIV0U/DIV0S instruction and updates D0/D1 flag to the same value
as 1.
• When user interrupt is generated, if you execute each instruction of ORCCR, STILM, MOV Ri or PS to
enable interrupt, the following operations are generated.
1. Updates PS register in first.
2. Executes EIT processing routine (user interrupt).
3. After returning from EIT, executes the instruction above and updates PS register to the same value as
1.
Note: For EIT, See “Chapter 6 EIT: Exceptions, Interrupts and Traps (Page No.121)”.