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Chapter 13 Clock Control
6.Settings
6. Settings
*: For the setting procedure, refer to the section indicated by the number.
*: For the setting procedure, refer to the section indicated by the number.
*: For the setting procedure, refer to the section indicated by the number.
*: For the setting procedure, refer to the section indicated by the number.
Table 6-1 Settings for Operating at 1/2 of the Main Clock
Setting Setting register
Setting
procedure*
Clock source selection Clock source control register (CLKR) See 7.3
Table 6-2 Settings for Operating Using the Main PLL
Setting Setting register
Setting
procedure*
Main PLL operation enable
Clock source control register (CLKR)
See 7.1
Clock source selection See 7.3
Table 6-3 Settings for Operating Using the Subclock
Setting Setting register
Setting
procedure*
Subclock selection enable
Clock source control register (CLKR)
See 7.1
Clock source selection See 7.3
Table 6-4 Settings for Selecting the Division Ratio for the Operating Clocks
Setting Setting register
Setting
procedure*
Clock source selection Clock source control register (CLKR) See 7.3
Operating clock division ratio selection
Operating clock division setting registers
(DIVR0, DIVR1)
See 7.4