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Chapter 11 Memory Controller
8.Explanations of Registers
WTP controls the wait timing of the FLASH access in case of page hit for Page Mode FLASH. The WTP
configuration is in units of clock cycles. The value of WTP should be set to the intra page access time
(cycle time) of the FLASH memory in number of clock cycles, subtracted by one.
The setting is used if the page size PS[2:0] is set different to 0.
• BIT[29:28]: WEXH[1:0] - Minimum WEX High timing requirement
WEXH is set to 3 after reset. The minimum high time duration of WEX is 5 cycles by default.
Setting an other value reduces the WEX high time to 2 fixed cycles + WEXH.
• BIT[27:24]: WTC[3:0] - Wait cycles for FLASH memory access
WTC is set to 15 after reset.
WTC controls the wait timing of the FLASH access. The WTC configuration is in units of clock cycles.
The value of WTC should be set to the access time (cycle time) of the FLASH memory in number of clock
cycles, subtracted by one.
• BIT[23]: FRAM - Wait cycles for F-Bus general purpose RAM memory access
FRAM is set to 0 after reset.
This is a reserved bit. This version on MB91V460 has no configurable wait timing to F-Bus RAM, it op-
erates with fixed 0 wait states RAM access.
• BIT[22:20]: ATD[2:0] - Duration of the ATDIN signal for FLASH memory access
MB91V460: ATD is set to 7 after reset. ATD defaults to 4 clock cycles.
MB91F467DA: ATD is set to 5 after reset. ATD defaults to 3 clock cycles.
ATD controls the timing of the ATDIN signal for FLASH access. The ATD configuration is in units of half
clock cycles. The effective high duration of ATDIN equals to tATDIN=(ATD+1)*0.5 clock cycles.
• BIT[19:16]: EQ[3:0] - Duration of the EQIN signal for FLASH memory access
MB91V460: EQ is set to 15 after reset. EQ defaults to 8 clock cycles.
MB91F467DA: EQ is set to 13 after reset. EQ defaults to 7 clock cycles.
EQ controls the timing of the EQIN signal for FLASH access. The EQ configuration is in units of half clock
cycles. The effective high duration of EQIN equals to tEQIN=(EQ+1)*0.5 clock cycles.
• BIT[14:12]: ALEH[2:0] - Duration of the ALEH time for FLASH memory access
MB91V460: not available
MB91F467DA: ALEH is set to 5 after reset. ALEH defaults to 3 clock cycles.
ALEH controls the timing of the ATDIN falling edge to EQIN rising edge for FLASH access.
The EQ configuration is in units of half clock cycles. The effective duration of ALEH equals to
tALEH=(ALEH+1)*0.5 clock cycles.
Important remark: ALEH[2:0] is updated automatically to the same value as ATD[2:0] when writing to
ATD[2:0]. Usually the ALEH time equals the ATD time, so there is normarlly no reason to update
ALEH[2:0] in particular.
Even though it is possible to program ALEH[2:0] with a different value than ATD[2:0] by:
- Writing a different value to ALEH[2:0] after writing to ATD[2:0], or
- Setting the FMCR.LOCK bit to disable the auto update