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Chapter 32 USART (LIN / FIFO)
4.USART Registers
Figure 4-1 Serial Control Register 04 (SCR04)
15 14 13 12 11 10 9 8
Initial value
0 0 0 0 0 0 0 0
B
R/W R/W R/W R/W WR/W R/W R/W
bit8
TXE Transmission enable
0 Disable Transmission
1 Enable Transmission
bit9
RXE Reception enable
0 Disable Reception
1 Enable Reception
bit10
CRE
Clear Reception errors
write read
0 ignored
read always returns 0
1 Clear all reception
errors (PE, FRE, ORE)
bit11
AD Address / Data bit
0 Data bit
1 Address bit
bit12
CL Character (Data frame) Length
0 7 bits
1 8 bits
bit13
SBL Stop bit length
0 1 stop bit
1 2 stop bits
bit14
P Parity setting
0 Even Parity enabled
1 Odd Parity enabled
bit15
PEN Parity Enable
0 Parity disabled
1 Parity enabled
R/W : Readable and writable
W : Write only
: Initial value