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Chapter 31 External Bus
8.Prefetch Operation
8. Prefetch Operation
This section explains the prefetch operation.
■ Prefetch Operation
The external bus interface controller contains a prefetch buffer consisting of 16 x 8 bits.
If the PSUS bit of the TCR register is 0 and read access to an area to which the PFEN bit of the ACR register is
set to 1 occurs, the subsequent address is prefetched and then stored in the prefetch buffer.
If the stored address is accessed from the internal bus, the lookahead data in the prefetch buffer is returned
without external access being performed. This can reduce the wait time for successive accesses to the external
bus areas.
● Basic conditions for starting external access using prefetch
External bus access using prefetch occurs when the following conditions are met:
• The PSUS bit of the TCR register is 0.
• Neither sleep mode nor stop mode is set.
• Read access by the external bus to a chip select area for which prefetch is enabled has been performed.
DMA access and read access by a read modified write system instruction, however, are excluded.
• No external bus access request (external bus area access to an area for which prefetch is not enabled or DMA
transfer with an external bus area) other than the prefetch access has occurred.
• The part of the prefetch buffer for the next operation of capturing the prefetch access is completely empty.
While the above conditions are met, the prefetch access will continue. If external bus area access to an area for
which prefetch is not enabled occurs after prefetch access, prefetch access to the area for which prefetch is
enabled will continue as long as the prefetch buffer clear conditions are not met.
For an access that mixes multiple prefetch-enabled areas and multiple prefetch-disabled areas, the prefetch
buffer always holds data of the prefetch-enabled area accessed last. Since, in this case, access to prefetch-
disabled areas does not affect the prefetch buffer state at all, data in the prefetch buffer is not wasted even if
prefetch-disabled data access and prefetch-enabled instruction fetch are mixed.
● Optional clear for temporary stopping of a prefetch access
Setting 1 for the PSUS bit of the TCR register temporarily stops a prefetch. The prefetch can be restarted by
setting the PSUS bit to 0. At this point, the contents of the buffer are retained if no error occurs or a buffer clear
such as occurs when the PCLR bit is set does not occur.
Setting 1 for the PCLR bit of the TCR register completely clears the prefetch buffer. Clear the buffer by setting
the PSUS bit when prefetch is interrupted.
Prefetch is temporarily stopped for the minimum unit (64 KB) of the boundary=chip select area where the high-
order 16 bits of an address change. If the boundary is crossed, first a buffer read error occurs and then prefetch
starts in a new area.
● Unit for one prefetch access operation
The unit for one prefetch access operation is determined by the DBW bits (bus width) and BST bits (burst length).
Prefetch access always occurs with the full size of the bus width specified by the DBW bits and access for the
count of the burst length set by the BST bits in one access operation is performed. That is, if any value other
than 00
B
is set for the BST bits, the prefetch always occurs in page mode/burst mode. Keep in mind whether
ROM/RAM is conformable and enough access time is applicable. (Set an appropriate value bits W15-08 bits of
the AWR register).