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Memory Management Unit (MMU)
82
NS9750 Hardware Reference
The translation process always begins in the same way — with a level-one fetch. A
section-mapped access requires only a level-one fetch, but a page-mapped access
requires an additional level-two fetch.
Translation table base
The hardware translation process is initiated when the TLB does not contain a
translation for the requested MVA. R2: Translation Table Base (TTB) register points to
the base address of a table in physical memory that contains section or page
descriptors, or both. The 14 low-order bits [13:0] of the TTB register are
UNPREDICTABLE on a read, and the table must reside on a 16 KB boundary.
Figure 24 shows the format of the TTB register.
Figure 24: R2: Translation Table base register
The translation table has up to 4096 x 32-bit entries, each describing 1 MB of virtual
memory. This allows up to 4 GB of virtual memory to be addressed.
31 014 13
Translation table base