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System control processor (CP15) registers
74
NS9750 Hardware Reference
See "R8:TLB Operations register" on page 68 for a description of the TLB-invalidate
operations.
Use these instructions to program the TLB Lockdown register:
The victim automatically increments after any table walk that results in an entry
being written into the lockdown part of the TLB.
Note:
It is not possible for a lockdown entry to map entirely either small or large
pages, unless all subpage access permissions are the same. Entries can
still be written into the lockdown region, but the address range that is
mapped covers only the subpage corresponding to the address that was
used to perform the page table walk.
Sample code sequence
This example shows the code sequence that locks down an entry to the current
victim.
ADR r1,LockAddr ; set R1 to the value of the address to be locked
down
MCR p15,0,r1,c8,c7,1 ; invalidate TLB single entry to ensure that
LockAddr is not already in the TLB
MRC p15,0,r0,c10,c0,0 ; read the lockdown register
ORR r0,r0,#1 ; set the preserve bit
MCR p15,0,r0,c10,c0,0 ; write to the lockdown register
LDR r1,[r1] ; TLB will miss, and entry will be loaded
MRC p15,0,r0,c10,c0,0 ; read the lockdown register (victim will have
; incremented
BIC r0,r0,#1 ; clear preserve bit
MCR p15,0,r0,c10,c0,0 ; write to the lockdown register
R11 and R12 registers
Accessing (reading or writing) these registers causes UNPREDICTABLE behavior.
Function Instruction
Read data TLB lockdown victim
MRC p15, 0, Rd, c10, c0, 0
Write data TLB lockdown victim
MCR p15, 0, Rd, c10, c0, 0