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Serial port control and status registers
664
NS9750 Hardware Reference
D18:17 R/W RDCR 00 Receive clock divide rate
00 1x clock mode (only NRZ or NRZI allowed)
01 8x clock mode
10 16x clock mode
11 32x clock mode
Determines the divide ratio for the receiver clock.
If the DPLL is not used, use the 1x clock mode value (00).
When the DPLL is used in the application, selecting
TDCR/RDCR is a function of the receiver encoding. The
NRXZ and NRZI modes can use the 1x configuration; all
other encoding must use the 8x, 16x, or 32x configuration
mode. The 8x configuration provides the highest possible
data rate; the 32x mode provides the highest possible
resolution.
The TMODE bit in this register is maintained for
NET+Arm family backward compatibility. When setting
the TDCR or RDCR register to a non-zero value, the
TMODE bit must be set to 1.When the TMODE, TDCR,
and RDCR fields are all set to 0, the port defaults to the
16x mode of operation.
D16 R/W TICS 0 Transmit internal clock source
0 Transmitter uses the bit-rate generator output for its
clock.
1 Transmitter uses the extracted clock provided by
DPLL.
Defines the transmit clock source when the TXSRC (D28)
field is set to 0.
There are two sources for internal clocks: the bit-rate
generator (BRG) and the receiver digital phase lock loop
(DPLL). The bit-rate generator uses a divider mechanism
for clock generation. The DPLL extracts the clock from
the incoming receive data stream.
Bits Access Mnemonic Reset Description
Table 387: Serial Channel B/A/C/D Bit-rate register