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BBus slave and DMA interface
680
NS9750 Hardware Reference
D13 R/W CPS 0x0 Connector PLH signal
0 Indicates to the host that this interface is not ready to
operate as an IEEE 1284 slave.
1 Indicates to the host that this interface is ready to
operate as an IEEE 1284 slave.
This bit should be set by software when the initialization
of the 1284 interface is complete.
D12 N/A Reserved N/A N/A
D11:10
D:09:08
R/W
R/W
FCRT
FDRT
0x3
0x3
Forward command ready threshold
(FwCmdReadyThreshold)
Forward data ready threshold (FwDatReadyThreshold)
00 4 bytes
01 8 bytes
10 16 or more bytes
11 28 or more bytes
Enables transfer from the corresponding FIFO. DMA is
inhibited until the FIFO contains the corresponding
number of bytes. Data in the FIFO beneath the threshold
is transferred only if the buffer gap timer is used.
D07:06 N/A Reserved N/A N/A
D05:04 R/W RRT 0x3 Reverse ready threshold (RvReadyThreshold)
00 1–4 bytes
01 5–8 bytes
10 13–16 bytes
11 29–32 bytes
Enables transfer from the corresponding FIFO. DMA is
inhibited until the FIFO can accept the corresponding
number of bytes.
D03 R/W FCM 0x0 Forward command mode (FwdCmdMode)
0 Direct CPU access
1 DMA control
D02 NA Reserved N/A N/A
D01 R/W FDM 0x0 Forward data mode (FwdDataMode)
0 Direct CPU access
1 DMA control
Bits Access Mnemonic Reset Description
Table 391: IEEE 1284 General Configuration register