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Memory Controller
Table 136 shows the outputs from the memory controller and the corresponding
inputs to the 512M SDRAM (64Mx8, pins 13 and 14 used as bank selects).
Output address
(ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 26 26
13 BA0 25 25
12 12 24 -
11 11 23 11
10 10/AP 22 AP
9 9 21 10
88 20 9
77 19 8
66 18 7
55 17 6
44 16 5
33 15 4
22 14 3
11 13 2
0 0 12 **
Table 136: Address mapping for 512M SDRAM (64Mx8, BRC)