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171
Memory Controller
Table 99 shows the outputs from the memory controller and the corresponding inputs
to the 256M SDRAM (8Mx32, pins 13 and 14 used as bank selects).
11 15 3
00 14 2
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 11 11
13 BA0 10 10
12 12 24 -
11 11 23 -
10 10/AP 22 AP
99 21 -
88 20 -
77 19 9
66 18 8
55 17 7
44 16 6
33 15 5
22 14 4
11 13 3
00 12 2
Table 99: Address mapping for 256 SDRAM (8Mx32, RBC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 98: Address mapping for 128 SDRAM (16Mx8, RBC)