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Caches and write buffer
110
NS9750 Hardware Reference
Figure 38 shows the ARM926EJ-S cache format.
Figure 38: ARM926EJ-S cache associativity
The following points apply to the ARM926EJ-S cache associativity:
The group of tags of the same index defines a set.
The number of tags in a set is the associativity.
The ARM926EJ-S caches are 4-way associative.
The range of tags addressed by the index defines a way.
The number of tags is a way is the number of sets, NSETS.
Table 47 shows values of S and NSETS for an ARM926EJ-S cache.
ARM926EJ-S S NSETS
4 KB 5 32
8 KB 6 64
16 KB 7 128
Table 47: Values of S and NSETS
0
1
2
3
4
5
6
7
n
TAG
1
2
31 0
Tag
Index Word Byte
S+5 1S+4 245
0
3