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Ethernet Communication Module
Ethernet Receive Status register
Address: A060 001C
The Ethernet Receive Status register contains the status for the last completed
receive frame. The RXBR bit in the Ethernet Interrupt Status register (see page 385)
is set whenever a receive frame is completed and the Ethernet Receive Status
register is loaded at the same time. Bits [15:0] are also loaded into the status field of
the receive buffer descriptor used for the frame.
Register bit assignment
D04 R Not used 0x0 Always set to 0.
D03:00 R TXCOLC 0x0 Transmit collision count
Number of collisions the frame incurred during
transmission attempts.
Bits Access Mnemonic Reset Description
Table 209: Ethernet Transmit Status register
Bits Access Mnemonic Reset Description
D31:27 N/A Reserved N/A N/A
D26:16 R RXSIZE 0x000 Receive frame size in bytes
Length of the received frame, in bytes.
Table 210: Ethernet Receive Status register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
ReservedRXCE RXDV RXOK RXBR RXMC Rsvd RXDR
Reserved RXSIZE