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Serial Control Module: UART
The next tables show sample UART baud rates. These rates can be produced using the
recommended PLL reference oscillator frequency of 29.4912 MHz and setting the
CLKMUX field in the Bit Rate register to 0. The first table shows the range of available
baud rates when the PLLND field in the PLL Configuration register is at least
0x13. The
second table shows the range of available baud rates when the PLLND field is less
then 0x13.
D20:19 R/W TDCR 00 Transmit clock divide rate
00 Not valid for UART
01 8x clock mode
10 16x clock mode
11 32x clock mode
Determines the divide ratio for the transmitter clock.
D18:17 R/W RDCR 00 Receive clock divide rate
00 Not valid for UART
01 8x clock mode
10 16x clock mode
11 32x clock mode
Determines the divide ratio for the receiver clock.
D16 R/W Not used 0 Always write 0 to this field.
D15 R/W Not used 0 Always write 0 to this field.
D14:00 R/W N 0x0000 Divisor value
Defines the divisor value used in the bit-rate generator to
determine effective frequency of the bit-rate generator.
The divisor value for UART operation is defined as
follows:
N = ((F
CLK
/ (UM * BR)) – 1)
where:
F
CLK
= Determined by CLKMUX field
UM = UartMode = 8, 16, or 32 as defined by RDCR
and TDCR
BR = BaudRate = Required baud rater
See Table 371 and Table 372 for examples.
Bits Access Mnemonic Reset Description
Table 370: Serial Channel B/A/C/D Bit-rate register