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149
Memory Controller
Byte lane control
The memory controller generates the byte lane control signals BLSOUT[3:0]_n according
to these attributes:
Little or big endian operation
AMBA transfer width, indicated by HSIZE[2:0]
External memory bank databus width, defined within each control register
The decoded HADDR[1:0] value for write accesses only
Word transfers are the largest size transfers supported by the memory controller. Any
access tried with a size greater that a word causes an error response. Each memory
chip select can be 8, 16, or 32 bits wide. The memory type used determines how the
WEOUT_n and BLSOUT_n signals are connected to provide byte, halfword, and word
access.
For read accesses, you must control the
BLSOUT_n signals by driving them all high or
all low. Do this by programming the byte lane state (PB) bit in the Static
Configuration [3:0] register. "Memory banks constructed from 8-bit or non-byte-
T4-T5 Static memory address, chip select, and control signals submitted to
static memory.
T5-T6 Read data returned from static memory. Data is provided to the AHB.
AHB write address provided to memory controller.
T6-T7 Turn around cycle 1.
T7-T8 Turn around cycle 2.
T8-T9 Static memory transfer address, chip select, and control signals
submitted to static memory.
Write enable inactive.
T9-T10 Memory controller processing.
T10-T11 Write enable taken active.
Write data submitted to static memory.
T11-T12 Static memory writes the data.
Write enable taken inactive.
Cycle Description
Table 78: Read followed by a write (all 0 wait state) with two turnaround cycles