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About the PCI-to-AHB Bridge
416
NS9750 Hardware Reference
PCI Revision ID register
Read-only value. To change this value, use the
REVISION_ID field in the PCI
Configuration 1 register in the PCI arbiter (see page 429).
PCI Class Code register
Read only value. To change this value, use the
CLASS_CODE field in the PCI
Configuration 1 register in the PCI arbiter (see page 429).
PCI Cache Size register
Read/write value that should always be set to
0x00. The bridge ignores this value.
PCI Latency Timer register
Read/write field programmed by the device driver.
PCI Header register
Read-only value, hardwired to
0x0.
D07 Hard-wired
to 1
FBBC 1 Fast back-to-back capable
0 No support
1 Support
Device supports fast back-to-back transactions as a
target only.
D06 N/A Not used 0 Hardwired to 0.
D05 Hard-wired
to 0
BS66 0 66MHz capable
Bus speed:
0 33 MHz
1 66MHz
D04:00 N/A Not used 0 Always set to 0.
Bits Access Mnemonic Reset Description
Table 256: PCI Status register