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683
IEEE 1284 Peripheral Controller
D07 R/C FDFBG 0x0 Forward data FIFO byte gap
(FwDatFifoByteGap)
The forward data byte gap timer expired and the buffer
closed. Set to 1 to clear this bit.
D06 R/C FCFBG 0x0 Forward command FIFO byte gap
(FwCmdFifoByteGap)
The forward command byte gap timer expired and the
buffer closed. Set to 1 to clear this bit.
D05 R/C FDFMB 0x0 Forward data FIFO max buffer
(FwDatFifoMaxBug)
The forward data maximum buffer length has been
reached and the buffer closed. Set to 1 to clear this bit.
D04 R/C FCFMB 0x0 Forward command FIFO max buffer
(FwCmdFifoMaxBuf)
The forward command maximum buffer length has been
reached and the buffer closed. Set to 1 to clear this bit.
D03 R/C FDFRI 0x0 Forward data FIFO ready interrupt
(FwDatFifoRdyInterrupt)
Contains data from the host. Set to 1 to clear this bit.
D02 R/C FCFRI 0x0 Forward command FIFO ready interrupt
(FwCmdFifoRdyInterrupt)
Contains data from the host. Set to 1 to clear this bit.
D01 R/C PC1I 0x0 Peripheral controller interrupt 1
Read the peripheral controller Interrupt Status register to
determine the source. Set to 1 to clear this bit.
D00 N/A Reserved 0x1 N/A
Bits Access Mnemonic Reset Description
Table 392: Interrupt Status and Control register