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721
USB Controller Module
Global Interrupt Status register
Address: 9010 0010
The Global Interrupt Status register contains the global interrupt status information.
All status bits are active high (1) and all interrupts that are serviced here are
cleared by writing a 1 to the appropriate field.
D17 R/W DMA4 0 DMA channel 4 interrupt
D16 R/W DMA3 0 DMA channel 3 interrupt
D15 R/W DMA2 0 DMA channel 2 interrupt
D14 R/W DMA1 0 DMA channel 1 interrupt
D13 R/W Not used 0 Always write to 0.
D12 R/W FIFO 0 Generate an interrupt when any FIFO interrupt Status field
is set and the corresponding interrupt is enabled using the
FIFO Interrupt Enable register.
D11 R/W URST 0 Generate an interrupt when the NS9750 is in device mode
and receives an interrupt from the host.
D10 R/W SOF 0 Generate an interrupt when the NS9750 is in device mode
and receives an SOF (start of frame) packet.
D09 R/W SUSPEND
(SSPND)
0 Generate an interrupt when the SUSPEND (SUSP) field in
the Global Interrupt Status register (see page 723) is
asserted.
D08 R/W SETINTF 0 Generate an interrupt when the SETINTF field in the
Global Interrupt Status register (see page 723) is asserted.
D07 R/W SETCFG 0 Generate an interrupt when the SETCFG in the Global
Interrupt Status register (see page 723) is asserted.
D06 R/W WAKEUP 0 Generate an interrupt when the WAKEUP field in the
Global Interrupt Status register (see page 723) is asserted.
D05:02 N/A Not used 0 Always write to 0.
D01 R/W OHCI_IRQ 0 Generate an interrupt when the OHCI_IRQ field in the
Global Interrupt Status register (see page 724) is asserted.
D00 N/A Not used N/A Always write to 0.
Bits Access Mnemonic Reset Description
Table 419: Global Interrupt Enable register