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377
Ethernet Communication Module
Transmit undersize frame counter (A060 0728)
Incremented for every frame less than 64 bytes, with a correct FCS value. This
counter also is incremented when a jumbo packet is aborted (see "TXAJ" on page 346)
and the MAC is not checking the FCS (see "CRCEN" on page 352), because the frame is
reported as having a length of 0 bytes.
Transmit fragment counter (A060 072C)
Incremented for every frame less than 64 bytes, with an incorrect FCS value.
General Statistics registers
Table 231 lists the General Statistics registers.
Carry Register 1 (CAR1) and Carry Register 2 (CAR2) have carry bits for all of the
statistics counters. These carry bits are set when the associated counter reaches a
rollover condition.
These carry bits also can cause the STOVFL (statistics counter overflow) bit in the
Ethernet Interrupt Status register (see "Ethernet Interrupt Status register" on page
385) to be set. Carry Register 1 Mask register (CAM1) and Carry Register 2 Mask
register (CAM2) have individual mask bits for each of the carry bits. When set, the
mask bit prevents the associated carry bit from setting the STOVFL bit.
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 TUND
D31:12 R Reset = Read as 0 Reserved
D11:00 R/W Reset = 0x000 TFRG
Address Register General registers R/W
A060_0730 CAR1 Carry Register 1 R
A060_0734 CAR2 Carry Register 2 R
A060_0738 CAM1 Carry Register 1 Mask register R/W
A060_073C CAM2 Carry Register 2 Mask register R/W
Table 231: General Statistics register address map