Filter
Top Products
www.digiembedded.com
445
PCI-to-AHB Bridge
D15 R/W CMS_CCD1 0 Allows the software to control the CCD1 bit
in the Cardbus Socket Present State register.
Reflects the current state of the CardBus
CCD#1 pin:
0 A card is inserted in the socket.
1 No card is in the socket.
Because CCD#1 can be shorted to either
CVS2 or CVS1, the value here applies when
CVS[2:1] are both 0.
D14:11 Hard-
wired to 0
Reserved N/A N/A
D10 R/W REQ_INTGT_EN 0 Enable for REQ_INTGATE interrupt
0 Disable interrupt (default)
1 Enable interrupt
D09
R/C
REQ_INTGATE 0 CardBus interrogate socket request
Set to 1 when a 1 is written to the CV_TEST
bit in the CardBus Force Event register. This
bit causes an interrupt to the CPU when the
REQ_INTGT_EN bit (D10 in this register) is
set.
D08 R/W INTERROGATE 0 Socket interrogation
0 Socket interrogation not in process
1 Socket interrogation on process
Set to 1 during socket interrogation, to
prevent changes in CCD#1, CCD#2, and
CSTSCHG# from affecting the values in the
CardBus Socket Event register.
D07 Hard-
wired to 0
Reserved N/A N/A
D06 R/W CCLKRUN_EN 0 CardBus CCLKRUN# enable
0 Attempt to negate CardBus CCLKRUN#
using CCLKRUN# protocol
1 Assert CardBus CCLKRUN#
D05 R/W CVS2 0 Value driven out on CVS2 pin during socket
interrogation.
Bits Access Mnemonic Reset Description
Table 279: CardBus Miscellaneous Support register