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System configuration registers
294
NS9750 Hardware Reference
Register bit assignment
Bits Access Mnemonic Reset Description
D31:10 N/A Reserved N/A N/A
D09:07 R/W LPCS 0x0 LCD panel clock select
000 AHB clock
001 AHB clock / 2
010 AHB clock / 4
011 AHB clock / 8
1xx LCD clock provided by external clock
D06 R/W BBC 0x1 BBus
0 Clock disabled
1 Clock enabled
D05 R/W LCC 0x1 LCD controller
0 Clock disabled
1 Clock enabled
D04 R/W MCC 0x1 Memory controller
0 Clock disabled
1 Clock enabled
D03 R/W PARBC 0x1 PCI arbiter
0 Clock disabled
1 Clock enabled
D02 R/W PC 0x1 PCI
0 Clock disabled
1 Clock enabled
D01 R/W Not used 0x0 Must be written to 0.
D00 R/W MACC 0x1 Ethernet MAC
0 Clock disabled
1 Clock enabled
Table 185: Clock Configuration register