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801
Timing
SDRAM burst write (32-bit)
Figure 109: SDRAM burst write (32-bit) timing
Notes:
1 This is the bank and RAS address.
2 This is the CAS address.
prechg active wr d-A data-B data-C data-D
M9
M8
M7
M6
M5
M4
M12M10
Note-1 Note-2
clk_out
data<31:0>
addr
data_mask<3:0>*
dy_cs_n<3:0>
ras_n
cas_n
we_n