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System configuration registers
284
NS9750 Hardware Reference
Timer 0–15 Reload Count registers
Address: A090 0044 (Timer 0) / 0048 / 004C / 0050 / 0054 / 0058 / 005C / 0060 / 0064 / 0068 /
006C / 0070 / 0074 / 0078 / 007C / 0080 (Timer 15)
The Timer Reload registers hold the up/down reload value.
Register bit assignment
D05:04 R/W BRF 0x0 Bandwidth reduction field
00 100%
01 75%
10 50%
11 25%
Programs the weight for each AHB bus master. Used to
limit the round robin scheduler.
D03:00 R/W HMSTR 0x0 hmaster
Program a particular AHB bus master number here. Note
that a particular master can be programmed to more than
one channel.
Bits Access Mnemonic Reset Description
Table 173: BRC0, BRC1, BRC2, BRC3 register
Bits Access Mnemonic Reset Description
D31:00 R/W TRCV 0x0 Timer Reload Count register value
Value loaded into the Timer register after the timer is
enabled and after the terminal count has been reached, if
the reload enable bit in the corresponding Timer Control
register is set.
Table 174: Timer Reload Count register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Timer reload count (TRCV)
Timer reload count (TRCV)