Filter
Top Products
www.digiembedded.com
125
Memory Controller
ROM, SRAM, and Flash
The memory controller uses the same read timing control for ROM, SRAM, and flash
devices. Each read starts with the assertion of the appropriate memory bank chip
select signals (
STCSOUT_n) and memory address (ADDROUT[27:0]). The read access time
is determined by the number of wait states programmed for the WAITRD field in the
Static Memory Read Delay register. The WAITTURN field in the Static Memory Turn
round Delay register determines the number of bus turnaround wait states added
between external read and write transfers.
Figure 41 shows an external memory read transfer with the minimum zero wait states
(
WA IT RD =0). Cycles T0 through T4 are internal AHB bus cycles. These cycles are
required to arbitrate for control of the AHB bus. Maximum performance is achieved
when accessing the external device with load multiple (LDM) or store multiple (STM)
CPU instructions. Table 49 provides the timing parameters. Table 50 describes the
transactions in Figure 41.
Figure 41: External memory 0 wait state read timing diagram
Timing parameter Value
WAITRD 0
WAITOEN 0
WAITPAGE N/A
WAITWR N/A
WAITWEN N/A
WAITTURN N/A
Table 49: Static memory timing parameters
clk_out
ADDR
DATAIN_n
STCSOUT_n
COEOUT_n
A
D(A)
T0 T1 T2 T3 T4 T5 T6