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285
System Control Module
Timer 0–15 Read register
Address: A090 0084 / 0088 / 008C / 0090 / 0094 / 0098 / 009C / 00A0 / 00A4 / 00A8 / 00AC / 00B0
/ 00B4 / 00B8 / 00BC / 00C0
The Timer Read registers read the current state of each Timer register.
Register bit assignment
Interrupt Vector Address Register Level 0–31
Address: A090 00C4 / 00C8 / 00CC / 00D0 / 00D4 / 00D8 / 00DC / 00E0 / 00E4 / 00E8 / 00EC /
00F0 / 00F4 / 00F8 / 00FC / 0100 / 0104 / 0108 / 010C / 0110 /
0114 / 0118 / 011C / 0120 / 0124 / 0128 / 012C / 0130 / 0134 / 0138 / 013C / 0140
The Interrupt Vector Address register configures the interrupt vector address for each
interrupt level source. There are 32 levels.
Bits Access Mnemonic Reset Description
D31:00 R TRR 0x0 Timer Read register
Reads the current state of each counter in a register.
Table 175: Timer Read register
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Timer read (TRR)
Timer read (TRR)
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Interrupt vector address register value (IVARV)
Interrupt vector address register value (IVARV)