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PCI bus arbiter
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NS9750 Hardware Reference
PCI Miscellaneous Support register
Address: A030 000C
The PCI Miscellaneous Support register contains miscellaneous PCI functions that are
required in NS9750.
Change the EN_BARx fields only during system initialization, when there is no
PCI activity.
In a system where NS9750 is not the host, the EN_BARx fields must be
programmed within 2
25
PCI clocks of RST# being negated. This is the time
allowed from
RST# negated to the first configuration cycle on the PCI bus.
D05 R/W EN_CCLKRUN 0 Enable CCLKRUN# interrupt
0 Disable (default)
1 Enable
D04 R/W EN_PCISERR 0 Enable SERR received from external PCI agent
0 Disable (default)
1 Enable
D03 R/W
EN_PBRK_M3
0 Enable external master 3 broken
0 Disable (default)
1 Enable
D02 R/W
EN_PBRK_M2
0 Enable external master 2 broken
0 Disable (default)
1 Enable
D01 R/W
EN_PBRK_M1
0 Enable external master 1 broken
0 Disable (default)
1 Enable
D00 R/W
EN_PBRK_M0
0 Enable PCI-to-AHB bridge broken
0 Disable (default)
1 Enable
BIts Access Mnemonic Reset Description
Table 262: PCI Arbiter Interrupt Enable register