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BBus slave and DMA interface
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NS9750 Hardware Reference
Register bit assignment
Bits Access Mnemonic Reset Description
D31:00 W RvFifoWriteReg N/A Write one to four bytes to the Reverse FIFO
when in CPU mode.
A FIFO entry containing one byte or two
bytes is written to Reverse FIFO Write
Register — Last.
A FIFO entry containing three bytes is
written in two steps:
Step 1: The lowest 16 bits are written to
the Reverse FIFO Register.
Step 2: The high byte is written to the
Reverse FIFO Write Register — Last.
A FIFO entry containing four bytes is
written to either register.
D31:00 W RvFifoWrite
Reg — Last
N/A
Table 396: Reverse Data FIFO Write register/Reverse Data FIFO Write Register — Last
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
RvFifoWriteReg - Last
RvFifoWriteReg - Last