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689
IEEE 1284 Peripheral Controller
Forward Command DMA Control register
Address: 9040 0024
The Forward Command DMA Control register controls when the Forward command
DMA buffer is closed, using two components:
16-bit maximum buffer counter. The maximum buffer counter increments
each time a DMA transfer occurs, by the number of bytes in the transfer.
The counter is reset each time a DMA is completed. If the counter reaches
or exceeds the forward command maximum buffer size
(FwCmdMaxBufSize), the 1284 module signals the DMA channel to close the
buffer and start a new one. A (maskable) interrupt is generated when
FwCmdMaxBufSize is reached. Future bytes are moved using DMA when the
next DMA is initiated by the DMA controller.
Note: This counter should not be set to a value greater than the buffer
length field value set in the 1284 forward command channel descriptor.
16-bit byte gap counter. The byte gap counter increments on each clock
cycle when a byte is not read from the host, with a maximum programmable
interval of 1.3 ms based on a 50 MHz BBus clock. The counter is reset when
a byte is read from the host. If the counter reaches the forward command
byte gap timeout (FwCmdByteGapTimer), the following occurs:
a Where the FIFOs are written with dwords containing four bytes each,
the gap timeout forces an incomplete dword (that is, 1–3 bytes) to be
written to the FIFO.
b Forward command FIFO ready, which usually means the threshold has
been met, is asserted. This results in continuation of the currently
active DMA until the FIFO is empty.
c When the data in the FIFO, including the incomplete dwords in Step 1,
is output through DMA, the DMA is terminated.
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31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
FwCmdMaxBufSize
FwCmdByteGapTimer