Filter
Top Products
Registers
234
NS9750 Hardware Reference
Static Memory Write Enable Delay 0–3 registers
Address: A070 0204 / 0224 / 0244 / 0264
The Static Memory Write Enable Delay 0–3 registers allow you to program the delay
from the chip select to the write enable assertion. The Static Memory Write Enable
Delay register is used in conjunction with the Static Memory Write Delay registers, to
control the width of the write enable signals. It is recommended that these registers
be modified during system initialization, or when there are no current or outstanding
transactions. Wait until the memory controller is idle, then enter low-power or
disabled mode.
Register bit assignment
Bits Access Mnemonic Description
D31:04 N/A Reserved N/A (do not modify)
D03:00 R/W WWEN Wait write enable (WAITWEN)
0000 One HCLK cycle delay between assertion of chip select
and write enable (reset value on reset_n).
0001–1111 (n+1) HCLK cycle delay, where the delay is
(WAITWEN+1) x t
HCLK
Delay from chip select assertion to write enable.
Table 160: Static Memory Write Enable Delay 0–3 registers
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
Reserved
Reserved WWEN