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Memory Controller
Table 55 provides the timing parameters. Table 56 describes the transactions for
Figure 44.
Figure 44: External memory 2 0 wait state read timing diagram
Timing parameter Value
WAITRD 0
WAITOEN 0
WAITPAGE N/A
WAITWR N/A
WAITWEN N/A
WAITTURN N/A
Table 55: Static memory timing parameters
Cycle Description
T0 AHB address provided to memory controller.
T0-T1 AHB transaction processing.
T1-T4 Arbitration of AHB memory ports.
T4-T5 Static memory address, chip select, and control signals submitted to
static memory.
T5-T6 Read data returned to static memory. Data is provided to the AHB.
T6-T7 AHB address provided to memory controller. AHB transaction
processing.
Table 56: External memory 2 0wait state reads
ADDR
DATAIN
STCSOUT_n
COEOUT_n
B
D(B)
A 0
D(A)
clk_out
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13