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Registers
210
NS9750 Hardware Reference
Dynamic Memory Refresh Timer register
Address: A070 0024
The Dynamic Memory Refresh Timer register configures dynamic memory operation.
It is recommended that this register be modified during system initialization, or when
there are no current or outstanding transactions. Wait until the memory controller is
idle, then enter low-power or disabled mode.These bits can, however, be changed
during normal operation if necessary.
Note:
The Dynamic Memory Refresh Timer register is used for all four dynamic
memory chip selects. The worst case value for all chip selects must be
programmed.
D02 R/W SR Self-refresh request (SREFREQ)
0 Normal mode
1 Enter self-refresh mode (reset value on
reset_n)
By writing 1 to this bit, self-refresh can be entered under software
control. Writing 0 to this bit returns the memory controller to normal
mode.
The self-refresh acknowledge bit in the Status register (see
page 207) must be polled to discover the current operating mode of
the memory controller.
Note: The memory controller exits from power-on reset with
the self-refresh bit on high. To enter normal functional
mode, set the self-refresh bit low. Writing to this register
with the bit set to high places the register into self-refresh
mode. This functionality allows data to be stored over
SDRAM self-refresh of the ASIC is powered down.
D01 R/W Not used Must write 1.
D00 R/W CE Dynamic memory clock enable
0 Clock enable if idle devices are deasserted to save power (reset
value on
reset_n)
1 All clock enables are driven high continuously.
Note: Clock enable must be high during SDRAM initialization.
Bits Access Mnemonic Description
Table 141: Dynamic Memory Control register