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About the PCI-to-AHB Bridge
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NS9750 Hardware Reference
About the PCI-to-AHB Bridge
The PCI-to-AHB bridge provides these features:
Supports PCI specification 2.1 and 2.2 protocol
AHB master and slave interfaces
PCI master and target interfaces
Open drain interrupt output for PCI bus
Interrupt to AHB bus for AHB and PCI bus errors
Supports 32-bit address and data on both busses
Supports AHB core clock up to 100 MHz, and a PCI core clock of 33 MHz
Performs all AHB-to-PCI reads as SPLIT transactions on the AHB bus
(improves bus use)
Supports AHB burst transfers up to 8 words
AHB master supports all AHB slave responses for upstream (initiated on the
PCI bus) PCI-to-AHB traffic
Supports early burst termination on the AHB bus
Dual 64-byte write buffers in both directions
Single 64-byte read buffers in both directions
Supports PCI configuration cycles
Supports target retry, target disconnect, and target abort on PCI bus
Supports all PCI parity generation and parity error detection
Includes all PCI-specific configuration registers
Supports configuration of internal PCI configuration registers using the AHB
bus
Supports PCI-to-AHB address translation
Supports AHB-to-PCI address translation
Note:
Use the AHB DMA function to move blocks of data between the ARM CPU
and the PCI bus. Do not use load and store multiple commands to the
PCI-to- AHB bridge and do not cache PCI memory.