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Dynamic memory controller
164
NS9750 Hardware Reference
devices. The row-bank-column address mapping scheme allows memory
accesses to be performed efficiently to nearby memory regions.
– 32-bit wide databus address mappings (BRC) (see "32-bit wide databus
address mappings (BRC)" on page 175). These address mappings are used for
32-bit data bus chip select with SDR-SDRAM or low power SDR-SDRAM. The
bank-row-column address mapping scheme allows the low-power SDR-
SDRAM memory features to be used efficiently.
– 16-bit wide databus address mappings, SDRAM (RBC) (see "16-bit wide
databus address mappings, SDRAM (RBC)" on page 185). These address
mappings are used for 16-bit data bus chip select with SDR-SDRAM memory
devices. The row-bank-column address mapping scheme allows memory
accesses to be performed efficiently to nearby memory regions.
– 16-bit wide databus address mappings (BRC) (see "16-bit wide databus
address mappings (BRC)" on page 193). These address mappings are used for
16-bit data bus chip select with SDR-SDRAM and low-power SDR-SDRAM. The
bank-row-column address mapping scheme allows the low-power SDR-
SDRAM memory features to be used efficiently.
32-bit wide databus address mappings, SDRAM (RBC)
Table 91 through Table 103 show 32-bit wide databus address mappings for several
SDRAM (RBC) devices.
Table 91 shows the outputs from the memory controller and the corresponding inputs
to the 16M SDRAM (1Mx16, pin 13 used as bank select).
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14---
13 BA 10 10
12---
11---
10 10/AP 21 AP
99 20 -
Table 91: Address mapping for 16M SDRAM (1Mx16, RBC)