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Ethernet Control and Status registers
368
NS9750 Hardware Reference
Statistics registers
Address: A060 0680 (base register)
The Statistics module has 39 counters and 4 support registers that count and save
Ethernet statistics. The Ethernet General Control Register #2 contains three Statistics
module configuration bits: AUTOZ, CLRCNT, and STEN. The counters support a “clear
on read” capability that is enabled when AUTOZ is set to 1.
Combined transmit and receive statistics counters
The combined transmit and receive statistics counters, listed in Table 228, are
incremented for each good or bad frame, transmitted and received, that falls within
the specified frame length limits of the counter (for example, TR127 counts 65–127
byte frames). The frame length excludes framing bits and includes the FCS
(checksum) bytes. All counters are 18 bits, with this bit configuration:
D31:18 R Reserved
D17:00 R/W Reset = 0x00000 Count (R/W)
Address Register Transmit and receive counters R/W
A060_0680 TR64 Transmit & receive 64 Byte frame counter R/W
A060_0684 TR127 Transmit & receive 65 to 127 Byte frame counter R/W
A060_0688 TR255 Transmit & receive 128 to 255 Byte frame counter R/W
A060_068C TR511 Transmit & receive 256 to 511 Byte frame counter R/W
A060_0690 TR1K Transmit & receive 512 to 1023 Byte frame counter R/W
A060_0694 TRMAX Transmit & receive 1024 to 1518 Byte frame counter R/W
A060_0698 TRMGV Transmit & receive 1519 to 1522 Byte good VLAN frame
count
R/W
Table 228: Combined transmit and receive statistics counters address map