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531
BBus Utility
Bits Access Mnemonic Reset Description
D31 R/W gpio31 0 gpio[31] control bit
D30 R/W gpio30 0 gpio[30] control bit
D29 R/W gpio29 0 gpio[29] control bit
D28 R/W gpio28 0 gpio[28] control bit
D27 R/W gpio27 0 gpio[27] control bit
D26 R/W gpio26 0 gpio[26] control bit
D25 R/W gpio25 0 gpio[25] control bit
D24 R/W gpio24 0 gpio[24] control bit
D23 R/W gpio23 0 gpio[23] control bit
D22 R/W gpio22 0 gpio[22] control bit
D21 R/W gpio21 0 gpio[21] control bit
D20 R/W gpio20 0 gpio[20] control bit
D19 R/W gpio19 0 gpio[19] control bit
D18 R/W gpio18 0 gpio[18] control bit
D17 R/W gpio17 0 gpio[17] control bit
D16 R/W gpio16 0 gpio[16] control bit
D15 R/W gpio15 0 gpio[15] control bit
D14 R/W gpio14 0 gpio[14] control bit
D13 R/W gpio13 0 gpio[13] control bit
D12 R/W gpio12 0 gpio[12] control bit
D11 R/W gpio11 0 gpio[11] control bit
D10 R/W gpio10 0 gpio[10] control bit
D09 R/W gpio9 0 gpio[9] control bit
D08 R/W gpio8 0 gpio[8] control bit
D07 R/W gpio7 0 gpio[7] control bit
D06 R/W gpio6 0 gpio[6] control bit
Table 326: GPIO Control Register #1