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Dynamic memory controller
196
NS9750 Hardware Reference
Table 130 shows the outputs from the memory controller and the corresponding
inputs to the 64M SDRAM (8Mx*, pins 13 and 14 used as bank selects).
44 13 5
33 12 4
22 11 3
11 10 2
009**
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
14 BA1 23 23
13 BA0 22 22
12---
11 11 21 -
10 10/AP 20 AP
99 19 -
88 18 9
77 17 8
66 16 7
55 15 6
44 14 5
33 13 4
22 12 3
11 11 2
0 0 10 **
Table 130: Address mapping for 64M SDRAM (8Mx8, BRC)
Output address
(
ADDROUT)
Memory device
connections
AHB address to row
address
AHB address to
column address
Table 129: Address mapping for 64M SDRAM (4Mx16, BRC)