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Registers
582
NS9750 Hardware Reference
LCDTiming1
Address: A080 0004
The LCDTiming1 register controls the vertical axis panel, which includes:
Number of lines-per-panel (LPP)
Vertical synchronization pulse width (VSW)
Vertical front porch (VFP) period
Vertical back porch (VBP period)
Register bit assignment
Bits Access Mnemonic Reset Description
D31:24 R/W VBP 0x00 Vertical back porch
Number of inactive lines at the start of a frame, after
vertical synchronization period. Program this field to
zero on passive displays, to avoid reduced contrast.
VBP specifies the number of line clocks inserted at
the beginning of each frame. The VBP count starts
just after the
CLFP for the previous frame has been
negated for active mode, or the extra horizontal
synchronization lines have been asserted as specified
by the VSW field in passive mode. After this occurs,
the count value in VBP sets the number of horizontal
synchronization lines inserted before the next frame.
VBP generates from
0 –255 extra line clock cycles.
Table 352: LCDTiming1 register
VBP
LPP
13121110987654321015 14
31 29 28 27 26 25 24 23 22 21 20 19 18 17 1630
VSW
VFP