Filter
Top Products
PCI bus arbiter
420
NS9750 Hardware Reference
If there are no new requesters when the current bus master completes its
transaction, the bus ownership stays with the most recent bus master (bus parking).
If a
REQ# is asserted from any of the other masters, there must be a one clock cycle
delay between the negation of the
GNT# to the parked bus master and the assertion of
the
GNT# to the bus master requesting the bus. If the granted bus master does not
start its bus transaction within 16 PCI clocks of the bus being idle, the PCI arbiter sets
the
PCIBRK_Mx bit for that master (in the PCI Arbiter Interrupt Status register; see
page 424) and negates
GNT#. The bus ownership can then be granted to one of the
other bus masters. For the three external masters,
REQ# from the broken master is
ignored until the interrupt service routine re-enables it by toggling its
PCIEN_Mx bit
from low-to-high in the PCI Arbitration Configuration register (see page 423).
(Although a broken master condition for the PCI-to-AHB bridge is logged using the
PCIBRK_Mx bit, it is never taken out of service.) The PCIEN_Mx bits are also used to
enable or disable the requests from the three external masters during normal
operation.
Slave interface
The PCI bus arbiter slave interface supports single 32-bit transfers only.
The system can be configured such that all CSRs can be accessed using only
“privileged mode” accesses (
HPROT=xx1x) or only user mode accesses (HPROT=xx0x). Use
internal register access mode bit 0 in the Miscellaneous System Configuration register
to set access accordingly (see "Miscellaneous System Configuration and Status
register" on page 296).
The slave generates a AHB bus error if the address is not aligned on a 32-bit boundary
and
Misaligned Bus Address Response Mode is set in the Miscellaneous System Configuration
and Status register. Accesses to non-existent addresses also result in an AHB bus error
response.
PCI Arbiter Configuration registers
Table 259 provides the PCI bus arbiter register map.