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621
Serial Control Module: UART
D12 R ROVER 0 Receive overrun
Indicates that a receive overrun error condition has been
found.
An overrun condition indicates that the FIFO was full
while data needed to be written by the receiver. When the
FIFO is full, any new receive data is discarded; the
contents of the FIFO prior to the overrun condition remain
the same. The receive data buffer is closed under this
condition.
In DMA mode, this field is copied to bit [0] in the DMA
buffer descriptor.
Be aware:
The overrun status may not be captured properly in the
status FIFO for a serial RX FIFO overrun. if this situation,
the overrun condition does not result in a buffer closure
and the overrun status bit is not set properly when the
receive data is read from the FIFO.
D11 R RRDY 0 Receive register ready
Indicates that data is available to be read from the FIFO
Data register. Before reading the FIFO Data register, the
RXFDB field in this (Serial Channel Status Register A)
register (see D21:20) must be read to determine how many
active bytes are available during the next read of the FIFO
Data register.
RRDY typically is used only in interrupt-driven
applications; this field is not used for DMA operation. The
RRDY status condition can be programmed to generate an
interrupt by setting the corresponding IE bit in Serial
Channel Control Register A.
The RRDY bit is never active when the RBC (D09) bit is
active. The RBC bit must be acknowledged by writing a 1
to the same bit position in this register to activate the
RRDY bit. When the receiver is configured to operate in
DMA mode, hardware automatically handles the interlock
between RBC and RRDY.
Bits Access Mnemonic Reset Description
Table 369: Serial Channel B/A/C/D Status Register A