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Registers
592
NS9750 Hardware Reference
D07 R/W LcdDual 0x0 LCD interface is dual panel STN
0 Single panel LCD is in use.
1 Dual panel LCD is in use.
D06 R/W LcdMono8 0x0 Monochrome LCD has 8-bit interface
0 Mono LCD uses 4-bit interface.
1 Mono LCD uses 8-bit interface.
Controls whether monochrome STN LCD uses a 4-
or 8-bit parallel interface. Program this bit to 0 for
other modes.
D05 R/W LcdTFT 0x0 LCD is TFT
0 LCD is STN display; use grayscaler.
1 LCD is TFT; do not use grayscaler.
D04 R/W LcdBW 0x0 STN LCD is monochrome (black and white)
0 STN LCD is color
1 STN LCD is monochrome
This bit has no meaning in TFT mode.
D03:01 R/W LcdBpp 0x00 LCD bits per pixel
000 1 bpp
001 2 bpp
010 4 bpp
011 8 bpp
100 16 bpp
101 24 bpp (TFT panel only)
110 Reserved
111 Reserved
D00 R/W LcdEn 0x0 LCD controller enable
0 LCD signals
CLLP, CLCP, CLFP, CLAC, and
CLLE disabled (held low).
1 LCD signals CLLP, CLCP, CLFP, CLAC, and
CLLE enabled (active).
See "LCD power up and power down sequence
support" on page 563 for more information about
LCD power sequencing.
Bits Access Mnemonic Reset Description
Table 358: LCDControl register