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timing diagram 831
IEEE 1284 General Configuration
register
679
IEEE 1284 timing 831
individual interrupts, LCD 566
industry-standard Ethernet interfaces
MII
315
RMII 315
initializing PLL parameters 14
initiating a DMA transfer, two channel
(AHB)
474
Int Config registers (0-31) 286
register address mapping 286
interrupt aggregation 483
INTERRUPT bit 476
interrupt bit 506
interrupt codes 553
Interrupt Configuration register 267
interrupt controller 267
-
270
FIQ interrupts 267
interrupt sources 268, 269
IRQ interrupts 267
vector interrupt controller 270
Interrupt Enable register 695
interrupt sources 268, 269
Interrupt Status Active register 289
Interrupt Status and Control register 681
interrupt status bits for DMA 536
Interrupt Status Raw register 290
Interrupt Status register 699
Interrupt Timeout Counter register 700
Interrupt Vector Address register 267
Interrupt Vector Address Register Level 0-
31
285
interrupts
CardBus
465
Ethernet 331
PCI 409, 458
interrupts, LCD 598
-
599
master bus error interrupt 598
next base address update
interrupt
599
vertical compare interrupt 598
IRQ interrupts 267
IRSADDR register 288
J
Jazelle (Java) 77
JTAG interface
pinout for ARM core/boundary scan
43
JTAG timing 836
L
L bit, Ethernet 328
LAST bit 476, 506
LCD controller 42, 559
-
599
about 559
AHB interface 568
-
579
dual DMA FIFOS and associated
control logic
568
external pad interface signals 575
generating interrupts 575
grayscaler 574
LCD panel signal multiplexing
details
575
master and slave interfaces 568
panel clock generator 574
pixel serializer 569
RAM palette 573
timing controller 574
upper and lower panel
formatters
574
clocks 565